1. Field of the Invention
The present invention relates to a lead frame for semiconductor packages and a method for plating the lead frame, and more particularly, to a pre-plated lead frame having an improved outermost plated layer over a metal substrate and a method for plating the lead frame.
2. Description of the Related Art
Lead frames, which form a semiconductor package together with a semiconductor chip, serve to support the semiconductor chip in the package in addition to electrically connecting the chip to an external circuit.
An example of a lead frame is shown in FIG. 1. As shown in FIG. 1, the lead frame 10 includes a pad 11, an inner lead 12 and an outer lead 13 The lead frame 10 is usually manufactured by stamping or etching.
FIG. 2 shows an example of a semiconductor package. As shown in FIG. 2, a semiconductor chip 15, which is mounted on the pad 11, is connected to the inner lead 12 by wire bonding. The outer lead 13 is electrically connected to an external circuit. The chip 15 and the inner lead 12 are molded with a resin 14, so that a semiconductor package 16 is completed.
In the manufacture of such a semiconductor package, edges of the pad 11 and inner lead 12 are plated with a metal such as silver (Ag) so as to improve the wire bonding properties between the chip 15 and the inner lead 12, and the characteristics of the pad 11. Also, for an improved solderability in mounting a semiconductor package onto a printed circuit board (PCB), solder containing tin (Sn) and lead (Pb) is deposited on a predetermined area of the outer lead 12. However, the plating and the soldering are carried out by wet processes after the molding with resin, so that the reliability problem rises.
To avoid this problem, use of a pre-plated frame has been suggested. According to the pre-plating technique, prior to semiconductor package process, plated layers are formed with a material having good solder wettability on a lead frame.
FIG. 3 shows an example of a lead frames manufactured by the conventional pre-plating technique. The conventional lead frame 20 shown in FIG. 3, which is disclosed in Japanese Patent No. 1501723, includes a nickel (Ni) plated layer 22 as an intermediate layer and a palladium (Pd) plated layer 23 as the outermost layer, which are sequentially formed on a metal substrate 21 made of copper (Cu) or copper alloy.
In the lead frame 20, the Ni plated layer 22 prevents diffusion of Cu or Fe of the metal substrate 21 up to the surface of the lead frame, by which copper oxide or copper sulfide are produced on the frame surface. Also, the Pd outermost plated layer 23 is formed of a good solderability material to provide a protective function for the surface of the nickel plate layer 22.
In the manufacture of the lead frame 20, a pre-treatment is carried out before plating. However, in the case where the surface of the metal substrate 21 has defects, due to a higher energy level in the defect region than in the other region having no defects, Ni plating for the Ni plated layer proceeds faster in the defect region than in the other region, resulting in a rough surface of the plated layer due to a decreased coherence with the other region. Especially, in the case where Pd is plated on the surface of the Ni plated layer formed on the defect region by electroplating, a large amount of hydrogen bubbles effervescing in electrolyte, are incorporated into the Pd plated layer during the plating with Pd. This is because the Pd deposition potential is similar to the hydrogen deposition potential. Accordingly, perforations due to the hydrogen bubbles are present boosting the defect problems with the Pd plated layer. Such defects in the Pd plated layer causes oxidation of the Ni plate layer, in addition to deteriorating the wire bonding and solderability properties. Besides such defects, a thermal process for semiconductor manufacture may cause interlayer diffusion in the lead frame in turn the solderability problems. Also, the surface of the Pd outermost plated layer can be oxidized by the thermal process, thereby deteriorating the inherent good solderability of palladium.
Another example of a lead frame manufactured by the pre-plating technique, which has been suggested so as to solve the above problems, is shown in FIG. 4. The lead frame 20xe2x80x2 shown in FIG. 4 further comprises a thin film 24 formed of gold (Au) on the Pd plated layer 23 compared to the lead frame 20 in FIG. 2. In the disclosure, Au having good oxidation resistance is used to plate the Pd plated layer so as to prevent oxidation of the Pd plated layer 23 with an improved solderability.
As described above, the plating of Au on the Pd plated layer is for preventing the oxidation of the Pd plated layer by the thermal process for semiconductor manufacture, thereby improving the solderability in mounting the completed package onto a PCB. In addition to the plating of Au, the topography of the Au plated layer is an important concern for improving the Au plating effects. However, a known Au plating technique is not sufficient to provide an even plated layer on the Pd plated layer. The Au plated layer is usually formed to a thickness of 0.3 microinch so as to prevent the oxidation of Pd. Unfortunately, such a thick Au plated layer brings an adverse impact into molding with EMC resin for semiconductor assembly, and particularly, in view of adhesion between the Au outermost plated layer of the lead frame and the molding resin. In molding with EMC resin, the EMS resin has a low affinity for a pure metal or alloy. Also, because Au has a greater oxidation resistance than Pd, the adhesion of the EMC mold to the Au plated layer is further decreased, causing mold delamination failure. Also, such poor adhesion between the Au plated layer and the resin lowers the reliability of the product.
In another aspect, forming such a thick Au plated layer is undesirable in view of costs. Also, the Au plate layer, which is formed as an anti-oxidation layer for Pd, relatively decreases the adhesion of a chip to a die. The Au plated layer can improve the solder wettiablity during soldering compared to a conventional lead frame. However, due to interaction between Au of the plated layer and tin (Sn) during the soldering process, the Au plated layer is easy to be broken by external impacts after being mounted on a PCB.
To account for these problems, localized plating, i.e., plating only the outer lead portion, has been suggested. However, the localized plating requires additional masks for the plating, which raises the manufacturing costs and lowers productivity. Due to this reason, the Au plate layer has been formed over the intermediate palladium plate layer so as to prevent the oxidation of the palladium plate layer, despite its costs.
U.S. Pat. No. 5,767,574 teaches a lead frame capable of eliminating the above problems, which includes a Ni alloy plated layer, a Pd strike plated layer and a Pd alloy layer which are sequentially formed on a metal substrate. Here, the outermost Pd alloy plated layer is composed of Pd and Au. The problem of the oxidation of Pd and the high cost of using Au can be eliminated by the outermost plated layer including Au. The restricted use of Au in the outermost layer improves the adhesion with resin in semiconductor packaging and minimizes the possibility of being broken after mounted on a PCB. However, when plating Au in the Pd-based outermost plate layer, it is difficult to effectively prevent the incorporation of hydrogen bubbles into the outermost layer. The presence of perforations due to hydrogen bubbles in the outermost layer deteriorates the outermost layer""s protective function for the underlying Pd plated layer. In addition to, the presence of the perforations degrades the wire bonding strength and solderability of the lead frame during thermal process.
To solve the above problems, it is an object of the present invention to provide a lead frame and a method for manufacturing the same, in which the solderability, wire bonding strength, the adhesion with resin in semiconductor packaging, and a protective function for a palladium (Pd) plated layer are improved.
The above object is achieved by the method according to the present invention for manufacturing a lead frame, the method comprising: forming a protective layer with nickel (Ni) or Ni alloy on a metal substrate; forming an intermediate layer with palladium (Pd) or Pd alloy on the protective layer; and alternately plating the surface of the intermediate layer with Pd and gold (Au) at least one time to form an outermost layer including both Pd and Au particles.
Preferably, the alternate plating to form the outermost layer, either Pd or Au can be plated first on the intermediated layer.
In the outermost plate layer formation, first Pd is roughly plated at the nucleation site of the intermediate layer by applying the pulse current, and in turn Au is accumulated filling the space between accumulated Pd particles. Because the Au deposition potential is lower than that the Pd deposition potential, Au particles can be easily accumulated between the Pd particles.
According to another aspect of the present invention, there is provided a lead frame for a semiconductor package, comprising: a protective layer formed of nickel (Ni) or Ni alloy on a metal substrate; an intermediate layer formed of palladium (Pd) on the protective layer; and an outermost layer formed of Pd and gold (Au) on the Pd intermediate layer.
In another embodiment, the present invention provides a lead frame for a semiconductor package, comprising: a protective layer formed of nickel (Ni) or Ni alloy on a metal substrate; and an outermost layer formed of palladium (Pd) and gold (Au) on the protective layer.
In the formation of the intermediate layer of Pd or Pd alloy and the Au or Au alloy plated regions, high pulse current application, sputtering or vapor deposition technique is used.